Low-Temperature Planar Polysilicon TFT Flash Memory Cell with Al2O3 Tunnel Dielectric and (Ti,Dy)xOy Control Dielectric For Three-Dimensional Integration

We report the fabrication process, material and electrical characterizations of ultra thin body (UTB) thin film transistors (TFTs) by using in situ doped polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 1019 cm-3 body doping. Root mean square (RMS) surface roughness below 1 nm is achieved over 25 μm2 area, tested by atomic force microscopy (AFM). The number density and average diameter of nanocrystals (NCs) embedded in a dielectric layer of the UTB TFT are 7.5 × 1011 cm-2 and 6.1 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM) is performed for material characterization. We obtain a memory window of about 3.8V by ± 6V program/erase (P/E) voltages. Therefore, UTB TFT becomes a promising candidate for the three dimensional (3D) integration in high-density nonvolatile memories.